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1. general description the 74lvc373a-q100 consists of eight d-type transparent latches, featuring separate d-type inputs for each latch and 3-state true outputs for bus-oriented applications. a latch enable input (pin le) and an output enable input (pin oe ) are common to all internal latches. when pin le is high, data at the d-inputs (p ins d0 to d7) enters the latches. in this condition, the latches are transparent, that is, a latch output changes each time its corresponding d-input changes. when pin le is low, the latches store the information that was present at the d-inputs one set-up time preceding the high-to-low transition of pin le. when pin oe is low, the contents of the ei ght latches are available at the q-outputs (pins q0 to q7). when pin oe is high, the outputs go to the high-impedance off-state. operation of input pin oe does not affect the stat e of the latches. inputs can be driven from either 3.3 v or 5 v devices. when disabled, up to 5.5 v can be applied to the outputs. these features allow the use of these devices as translators in mixed 3.3 v and 5 v applications. the 74lvc373a-q100 is functionally identical to the 74lvc573a-q100, but has a different pin arrangement. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? 5 v tolerant inputs/outputs for interfacing with 5 v logic ? wide supply voltage range from 1.2 v to 3.6 v ? cmos low power consumption ? direct interface with ttl levels ? high-impedance outputs when v cc = 0 v ? complies with jedec standard: ? jesd8-7a (1.65 v to 1.95 v) ? jesd8-5a (2.3 v to 2.7 v) ? jesd8-c/jesd36 (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 74lvc373a-q100 octal d-type transparen t latch with 5 v tolerant inputs/outputs; 3-state rev. 1 ? 17 april 2013 product data sheet
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 2 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvc373ad-q100 ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74LVC373ADB-Q100 ? 40 ? c to +125 ? c ssop20 plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 74lvc373apw-q100 ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74lvc373abq-q100 ? 40 ? c to +125 ? c dhvqfn20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 ? 4.5 ? 0.85 mm sot764-1 fig 1. logic symbol fig 2. iec logic symbol mna881 d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 q7 le 11 1 18 17 14 13 8 7 4 3 19 16 15 12 9 6 5 2 oe mna880 19 16 15 12 9 6 5 1 en 11 c1 1d 2 18 17 14 13 8 7 4 3
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 3 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state fig 3. functional diagram fig 4. logic diagram for one latch mna882 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 19 16 15 12 9 6 5 2 d0 d1 d2 d3 d4 d5 d6 d7 le oe 18 11 1 17 14 13 8 7 4 3 q le d le le le mna189 fig 5. logic diagram mna883 q4 d4 d le q q3 d3 d le q q2 d2 d le q q1 d1 d le lele q q0 d0 dq le oe le le le le q5 d5 d le q le q6 d6 d le q le q7 d7 d le q le
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 4 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 5. pinning information 5.1 pinning 5.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 6. pin configuration for so20 and (t)ssop20 fig 7. pin configuration for dhvqfn20

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&' table 2. pin description symbol pin description oe 1 output enable input (active low) le 11 latch enable input (active high) d[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 latch output gnd 10 ground (0 v) v cc 20 supply voltage
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 5 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 6. functional description [1] h = high voltage level h = high voltage level one set-up time prior to the high-to-low le transition l = low voltage level l = low voltage level one set-up time prior to the high-to-low le transition z = high-impedance off-state 7. limiting values [1] the minimum input voltage ratings may be excee ded if the input current ratings are observed. [2] the output voltage ratings may be exceeded if the output current ratings are observed. [3] for so20 packages: above 70 ? c the value of p tot derates linearly with 8 mw/k. for (t)ssop20 packages: above 60 ? c the value of p tot derates linearly with 5.5 mw/k. for dhvqfn20 packages: above 60 ? c the value of p tot derates linearly with 4.5 mw/k. table 3. functional table [1] operating modes input internal latch output oe le dn qn enable and read register (transparent mode) lhlll lhhhh latch and read register l l l l l llhhh latch register and disable outputs hl l l z hl h hz table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v i ik input clamping current v i < 0 ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o > v cc or v o < 0 - ? 50 ma v o output voltage high or low-state [2] ? 0.5 v cc + 0.5 v 3-state [2] ? 0.5 +6.5 v i o output current v o = 0 v to v cc - ? 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [3] -500 mw
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 6 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 8. recommended operating conditions 9. static characteristics table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 1.65 - 3.6 v functional 1.2 - - v v i input voltage 0 - 5.5 v v o output voltage high or low-state 0 - v cc v 3-state 0 - 5.5 v t amb ambient temperature in free air ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v cc = 1.65 v to 2.7 v 0 - 20 ns/v v cc = 2.7 v to 3.6 v 0 - 10 ns/v table 6. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max v ih high-level input voltage v cc = 1.2 v 1.08 - - 1.08 - v v cc = 1.65 v to 1.95 v 0.65 ? v cc - - 0.65 ? v cc -v v cc = 2.3 v to 2.7 v 1.7 - - 1.7 - v v cc = 2.7 v to 3.6 v 2.0 - - 2.0 - v v il low-level input voltage v cc = 1.2 v - - 0.12 - 0.12 v v cc = 1.65 v to 1.95 v - - 0.35 ? v cc -0.35 ? v cc v v cc = 2.3 v to 2.7 v - - 0.7 - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il i o = ? 100 ? a; v cc =1.65vto3.6v v cc ? 0.2 - - v cc ? 0.3 - v i o = ? 4ma; v cc = 1.65 v 1.2 - - 1.05 - v i o = ? 8ma; v cc = 2.3 v 1.8 - - 1.65 - v i o = ? 12 ma; v cc = 2.7 v 2.2 - - 2.05 - v i o = ? 18 ma; v cc = 3.0 v 2.4 - - 2.25 - v i o = ? 24 ma; v cc = 3.0 v 2.2 - - 2.0 - v v ol low-level output voltage v i =v ih or v il i o = 100 ? a; v cc = 1.65 v to 3.6 v - - 0.2 - 0.3 v i o =4ma; v cc = 1.65 v - - 0.45 - 0.65 v i o =8ma; v cc = 2.3 v - - 0.6 - 0.8 v i o =12ma; v cc = 2.7 v - - 0.4 - 0.6 v i o =24ma; v cc = 3.0 v - - 0.55 - 0.8 v i i input leakage current v cc = 3.6 v; v i =5.5vorgnd - ? 0.1 ? 5- ? 20 ? a
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 7 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state [1] all typical values are measured at v cc = 3.3 v (unless stated otherwise) and t amb =25 ? c. 10. dynamic characteristics i oz off-state output current v i =v ih or v il ; v cc = 3.6 v; v o =5.5vorgnd; - ? 0.1 ? 5- ? 20 ? a i off power-off leakage current v cc = 0 v; v i or v o = 5.5 v - ? 0.1 ? 10 - ? 20 ? a i cc supply current v cc = 3.6 v; v i =v cc or gnd; i o =0a -0.110 - 40 ? a ? i cc additional supply current per input pin; v cc = 2.7 v to 3.6 v; v i =v cc ? 0.6 v; i o =0a - 5 500 - 5000 ? a c i input capacitance v cc = 0 v to 3.6 v; v i =gndtov cc -5.0- - -pf table 6. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v). for test circuit see figure 12 . symbol parameter conditions ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max t pd propagation delay dn to qn; see figure 8 [2] v cc = 1.2 v - 14 - - - ns v cc = 1.65 v to 1.95 v 1.5 6.5 15.8 1.5 18.2 ns v cc = 2.3 v to 2.7 v 1.0 3.4 8.2 1.0 9.4 ns v cc = 2.7 v 1.5 3.4 7.8 1.5 10.0 ns v cc = 3.0 v to 3.6 v 1.5 2.9 6.8 1.5 8.5 ns le to qn; see figure 9 [2] v cc = 1.2 v - 16 - - - ns v cc = 1.65 v to 1.95 v 2.2 7.3 16.8 2.2 19.3 ns v cc = 2.3 v to 2.7 v 1.5 3.9 8.6 1.5 10.0 ns v cc = 2.7 v 1.5 3.5 8.2 1.5 10.5 ns v cc = 3.0 v to 3.6 v 1.5 3.3 7.2 1.5 9.0 ns t en enable time oe to qn; see figure 10 [2] v cc = 1.2 v - 17 - - - ns v cc = 1.65 v to 1.95 v 1.5 6.8 17.6 1.5 20.3 ns v cc = 2.3 v to 2.7 v 1.5 3.8 9.7 1.5 11.2 ns v cc = 2.7 v 1.5 3.8 8.7 1.5 11.0 ns v cc = 3.0 v to 3.6 v 1.5 3.1 7.7 1.5 10.0 ns
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 8 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state [1] typical values are measured at t amb =25 ? c and v cc = 1.2 v, 1.8 v, 2.5 v, 2.7 v and 3.3 v respectively. [2] t pd is the same as t plh and t phl . t en is the same as t pzl and t pzh . t dis is the same as t plz and t phz . [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in volts n = number of inputs switching ? (c l ? v cc 2 ? f o ) = sum of the outputs t dis disable time oe to qn; see figure 10 [2] v cc = 1.2 v - 8.0 - - - ns v cc = 1.65 v to 1.95 v 2.3 4.3 10.3 2.3 11.9 ns v cc = 2.3 v to 2.7 v 1.0 2.4 5.8 1.0 6.8 ns v cc = 2.7 v 1.5 3.2 7.1 1.5 9.0 ns v cc = 3.0 v to 3.6 v 1.5 3.0 6.1 1.5 8.0 ns t w pulse width le high; see figure 9 v cc = 1.65 v to 1.95 v 5.0 - - 5.0 - ns v cc = 2.3 v to 2.7 v 4.0 - - 4.0 - ns v cc = 2.7 v 3.0 - - 3.0 - ns v cc = 3.0 v to 3.6 v 3.0 1.5 - 3.0 - ns t su set-up time dn to le; see figure 11 v cc = 1.65 v to 1.95 v 4.0 - - 4.0 - ns v cc = 2.3 v to 2.7 v 3.0 - - 3.0 - ns v cc = 2.7 v 2.0 - - 2.0 - ns v cc = 3.0 v to 3.6 v 2.0 0.0 - 2.0 - ns t h hold time dn to le; see figure 11 v cc = 1.65 v to 1.95 v 3.0 - - 3.0 - ns v cc = 2.3 v to 2.7 v 2.0 - - 2.0 - ns v cc = 2.7 v 1.5 - - 1.5 - ns v cc = 3.0 v to 3.6 v 1.5 0.3 - 1.5 - ns t sk(o) output skew time v cc = 3.0 v to 3.6 v [3] - - 1.0 - 1.5 ns c pd power dissipation capacitance per latch; v i = gnd to v cc [4] v cc = 1.65 v to 1.95 v - 16.6 - - pf v cc = 2.3 v to 2.7 v - 19.2 - - pf v cc = 3.0 v to 3.6 v - 21.6 - - pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v). for test circuit see figure 12 . symbol parameter conditions ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 9 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 11. ac waveforms measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 8. input (dn) to output (qn) propagation delays mna884 dn input qn output t phl t plh gnd v i v m v m v oh v ol measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 9. latch enable input (le) pulse width, the latch enable input to output (qn) propagation delays mna885 le input qn output t phl t plh t w v m v oh v i gnd v ol v m
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 10 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state measurement points are given in table 8 . v ol and v oh are typical output voltage levels that occur with the output load. fig 10. 3-state enable and disable times mna886 t plz t phz output disabled output enabled v y v x output enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v ol v oh v cc v i v m gnd gnd t pzl t pzh v m v m measurement points are given in table 8 . the shaded areas indicate when the input is per mitted to change for predictable output performance. fig 11. data set-up and hold times for the dn input to the le input mna887 t h t su t h t su v m v m v i gnd v i gnd le input dn input table 8. measurement points supply voltage input output v cc v i v m v m v x v y 1.2 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 1.65 v to 1.95 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.3 v to 2.7 v v cc 0.5 ? v cc 0.5 ? v cc v ol + 0.15 v v oh ? 0.15 v 2.7 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v 3.0 v to 3.6 v 2.7 v 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 11 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state test data is given in table 9 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 12. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 9. test data supply voltage input load v ext v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 1.2 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 1.65 v to 1.95 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 2.3 v to 2.7 v v cc ? 2 ns 30 pf 500 ? open 2 ? v cc gnd 2.7v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd 3.0vto3.6v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 12 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 12. package outline fig 13. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z ywv references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 13 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state fig 14. package outline sot339-1 (ssop20) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p q (1) zywv references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 8 0 o o 0.13 1.25 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot339-1 mo-150 99-12-27 03-02-19 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 11 0 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 a max. 2
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 14 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state fig 15. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 15 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state fig 16. package outline sot764-1 (dhvqfn20) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 16 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model mil military mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74lvc373a_q100 v.1 20130417 product data sheet - -
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 17 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvc373a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 17 april 2013 18 of 19 nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc373a-q100 octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 april 2013 document identifier: 74lvc373a_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 17 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 contact information. . . . . . . . . . . . . . . . . . . . . 18 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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